`include "define.v"
module SoC_tb;
reg clk,rst;

SOC soc0(
.clk(clk),
.rst(rst)
);


initial 
	begin
	clk=0;
	rst=`Enable;
	#100 rst=`Disenable;
	#2000 $stop;
	end

always #10 clk=~clk;

endmodule 

